The constant movement of data (e.g., video data) at various memory hierarchies of on-chip network architectures increases the memory bandwidth (i.e., the rate at which the data is read from or stored into memory) as well as power consumption. To reduce memory bandwidth and power consumption, the data is typically encoded (e.g., compressed) using any number of different types of encoding (e.g., compression) techniques.
Conventional encoding techniques include compressing data at various stages of a data processing pipeline. For example, link compression techniques compress data at one side of link (e.g., a bus) and then transmit the compressed to another side of the link, where the compressed data is decompressed and stored in memory (e.g., cache memory). Link compression shares a model of the data at the encoding and decoding sides of the on-chip links to provide a high compression ratio (e.g., ratio between the uncompressed size of data and compressed size of the data or ratio between compressed data rate and uncompressed data rate), reducing the amount of data (or data rate) sent between links.